Several input/output (I/O) level interfaces are available to a chip designer to select from in designing an integrated circuit that is operable with an external chip. Choices in the selection of various I/O level interfaces raise the possibility of incompatibility problems in voltage signal handshakes between different semiconductor chips. Several types of I/O level interfaces are available on the market which include transistor-transistor logic (TTL), Low Voltage TTL (LVTTL), and Stub Series Terminated Logic (SSTL) interfaces.
A conventional solution to solve incompatible I/O interfaces between multiple chips is to design an integrated circuit that contains multiple I/O interfaces such that each interface within the integrated circuit operates to communicate with a particular type of I/O level interface. This solution is cumbersome and inefficient. The overall dimension of a die increases due to the additional circuitry required for a separate and dedicated interface for each type of I/O level interface. A larger die increases the manufacturing costs, the cost to distributors, as well as reduces sales. Secondly, this design requires a multiplexer to select from one of the I/O level interfaces, which enlarges the circuitry and adds additional delay. The speed penalty imposed from the added delay of the multiplexer produces a speed path which is inefficient. Although the speed penalty of the multiplexer can be overcome by manufacturing each I/O interface on a separate metal mask, the separate metal mask adds to the total manufacturing costs. Separate metal masks also impose on the selection of a particular type I/O level interface during the early stages of a chip design to ensure the manufacturing feasibility once the chip is ready for mass production.
Another conventional solution implements an input receiver by adding or removing field-effect-transistors (FET) as needed for a particular type of I/O level interface. The type of interface TTL, LVTTL, or SSTL, will dictate the number and/or sizes of the FET transistors inserted or removed in the input receiver. The additional FET transistors are placed either in series or in parallel with the existing circuitry in an input receiver in order to achieve the necessary voltage requirements for a particular type of I/O level interface. A drawback of this approach is that the switching speed of an input receiver can be negatively impacted when some of the FET transistors are not operational in the input receiver.
A further solution implements an input receiver in a ratio logic configuration as shown in FIG. 1. A ratio logic input receiver 1 includes a P-channel FET (PFET) transistor 2 coupled in series to a NFET transistor 3 in an inverter-like structure. The trip point of the ratio logic input receiver 1 is determined from a Vdd voltage. A trip or switching point represents a voltage level where an input receiver will recognize an input signal as a high signal or a low signal. The trip point in the ratio logic input receiver 1 can be tuned and adjusted by changing the sizes of the PFET transistor 2 and NFET transistor 3. A short-coming of the ratio logic input receiver 1 is that the trip point can fluctuate widely between high and low Vdd voltages. The wide swing in receiver switch point between high and low Vdd voltages deters a chip designer from using the ratio logic input receiver 1 for fast speed devices and renders the utilization of the ratio input logic receiver 1 more suitable for slower speed devices.
Accordingly, it is desirable to have an input receiver capable of communicating with multiple I/O level interfaces at fast speed and lower cost.